Liquid crystal display having pad parts and method for manufacturing the same

ABSTRACT

A flat panel display, such as an LCD, has a substrate for fabricating thereon pixel electrodes and data and gate lines which are connected to pad terminals to communicate electronic signals to and from the display panel. To enhance the contact between the pad terminals to outer devices, such as display drivers, a plurality of holes are created near the pad terminals of the display panel to adhere the tape carrier package (TCP) to the substrate of the display panel. The TCP securely attached to the substrate prevents the passivation layer of the pixel electrodes from being disturbed from its original configuration or peeled off from the substrate.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method for manufacturing aliquid crystal display (LCD) device, and in particular, the presentinvention relates to a method for an LCD in which the pad terminalcommunicating the electric signal with the outer device and the terminalof the outer device are cohering well each other and to the structure ofan LCD having the same pad terminal.

[0003] 2. Description of Related Art

[0004] The cathode ray tube (CRT), the most widely used display device,is being replaced by the thin flat display device because the flatdisplay device is thinner and lighter than the CRT so it can be appliedto any place. Active research activities have focused on the developmentof liquid crystal display devices because of their high resolution andfast response time suitable for displaying motion picture images.Furthermore, the active panel comprising an active switching elementsuch as a thin film transistor (or TFT) is more popularly applied to theLCD.

[0005] A liquid crystal display device works by using polarization andoptical anisotropy of a liquid crystal. By controlling the orientationof liquid crystal molecules having rod shape through polarizationtechnique, transmission and interception of a light through the liquidcrystal are achieved due to the anisotropy of the liquid crystal. Thisprinciple is applied to the liquid crystal display device. Active matrixLCDs (AMLCDs) having TFTs arranged in a matrix pattern and pixelelectrodes connected to the TFTs provide high quality images and are nowwidely used.

[0006] The structure of a conventional AMLCD will now be described. FIG.1 shows a perspective view of the AMLCD and FIG. 2 shows thecross-sectional view of FIG. 1 along the cutting line II-II. Theconventional AMLCD comprises an upper panel 3 and a lower panel 5 whichare joined to each other with a liquid crystal material 10 injectedtherebetween. The upper panel 3 has a color filter panel which includesa sequential arrangement of red(R), green(G) and blue(B) color filters 7on a first transparent substrate 1 a at pixel positions designed in amatrix pattern. Among these color filters 7, black matrixes 9 are formedin a lattice pattern. The black matrixes 9 prevent the colors frommixing at the boundary area. On the color filters 7, a common electrode8 is formed. The common electrode 8 is one electrode of the twoelectrodes generating an electric field applied to the liquid crystallayer.

[0007] The lower panel 5 of the LCD comprises switching elements and buslines generating the electric field for driving the liquid crystallayer. This panel is called an active panel. The active panel 5 of anAMLCD includes pixel electrodes 47 designed in a matrix pattern andformed on a second transparent substrate 1 b. Along the column directionof the pixel electrodes 41, signal bus lines 13 are formed, and alongthe row direction of the pixel electrodes 47, data bus lines 23 areformed. At a corner of a pixel electrode 47, a TFT 19 for driving thepixel electrode 47 is formed. A gate electrode 11 of the TFT 19 isconnected with the signal bus line 13 (or the gate line). A sourceelectrode 21 of the TFT 19 is connected with the data bus line 23 (orthe source line). A semiconductor layer 33 is formed between the sourceelectrode 21 and the drain electrode 31. The source electrode 21 and thesemiconductor layer 33 are ohmic contacted to each other. The drainelectrode 31 and the semiconductor layer 33 are also ohmic contacted. Agate pad 15 and a source pad 25, the terminals of the bus lines, areformed at the end portion of the gate line 13 and the source line 23,respectively. Additionally, a gate pad terminal 57 and a source padterminal 67 are formed on the gate pad 15 and the source pad 25,respectively.

[0008] As signal voltage applied to the gate pad 15 is applied to thegate electrode 11 via the gate line 13, the TFT 19 of the correspondedgate electrode 11 is in the ON state. Then the source electrode 21 andthe drain electrode 31 of the TFT 19 are electrically connected so thatthe electrical picture data applied source pad 25 is sent to the drainelectrodes 27 through the source line 23 and the source electrode 21.Therefore, by controlling the signal voltage to the gate electrode 11,the transfer of picture data to the drain electrode is controlled. Thatis, the TFT 19 acts as a switching element. A gate insulating layer 17is inserted between the layer including the gate electrode 13 and thelayer including the source electrode 23 to electrically isolate them. Apassivation layer 37 is formed on the layer including the source line 23to protect all elements of the transistor.

[0009] The color filter panel 3 and the active panel 5 are bondedtogether to face each other with a certain separation distancetherebetween (i.e., a cell gap). Liquid crystal material 10 fills thecell gap and the edge of the bonded panels is sealed with a sealant 81such as an epoxy to prevent the liquid crystal from leaking out so thata liquid crystal panel of an AMLCD is completed.

[0010] The AMLCD is finally made by assembling the liquid crystal panelwith peripheral devices for the screen data. At this time, the pads ofthe liquid crystal panel and the terminal of the peripheral devices aregenerally electrically connected with a tape carrier package (TCP) usingan anisotropic conductive film (ACF). FIG. 3 shows a general structureof the ACF. FIGS. 4a and 4 b illustrate the conventional method forconnecting the TCP to the pad using the ACF and illustrate the structureof the pad.

[0011] As shown in FIG. 3, the ACF 71 comprises a plurality ofconductive ball 95 coated with an insulation membrane 93 in an isotropicfilm 31. On the pad terminals 47 connected to the pads 45 (for example,the gate pads 15 or the source pad 25) arraying at the edge of theliquid crystal panel, an ACF 71 is attached and TCP 73 is sequentiallyattached thereon. At this time, the conductive pad 75 of the TCP 73should be aligned with the pad 45 (for example, the gate pads 15 or thesource pad 25) of the liquid crystal panel, as shown in FIG. 4a. The TCP73 is pressed and heated while the conductive balls 95 are insertedbetween the TCP pad 75 and the pad terminal 47 of the liquid crystalpanel. When sufficient pressure is applied against the TCP 73, theinsulation membrane 93 covering the conductive ball 95 are broken sothat the each TCP pad 75 is electrically connected to each pad terminal47 of the liquid crystal panel, as shown in FIG. 4b. Even if there aresome conductive balls 95 between the neighbored pad terminals 47, theneighbored pad terminals 47 are electrically isolated to each otherbecause the conductive balls 95 are covered by the insulation membrane93.

[0012] In the step of attaching the TCP to the pad terminal as mentionedabove, the film portion 77 between each pad portion 73 are expandedsomewhat by heat and pressure and cohered to the passivation layer 37formed on the top of the liquid crystal panel. As shown in FIG. 5, afterremoving the pressure and the heat, the expanded film portion of the TCPis shrunk which results in the pulling force 83 so that the passivationlayer 37 being cohered with the film portion 77 is peeled off.

[0013] Generally, after the liquid crystal panel is completed, the edgeportion of the panel having the shorting bar used for protecting theelectrostatic need to be trimmed off. At that time, the trimming force,which is applied to the trimmed edge, can cause the passivation layer 37or the gate insulating layer 17 to be structurally unstable. At thisportion, the passivation layer 37 can be easily peeled off, when theheating energy is removed after the film portion 77 of the TCP iscohered with the passivation layer 37 with the ACF 71 therebetween. Thiscomes from the peeling force 89 made of the vector summation of thehorizontal shrinking force 87 of the ACF 71 and the vertical shrinkingforce 85 of the ACF 71 and TCP 73, as shown in FIG. 6.

SUMMARY OF THE INVENTION

[0014] It is an object of the present invention to suggest a method formanufacturing the LCD panel with enhanced structural integrity of theLCD panel in which the coherence of the TCP and the LCD panel isenhanced when the TCP is attached to the pad terminals of the LCD forelectrically connecting them.

[0015] Another object is to suggest a method for manufacturing the LCDpanel in which the ACF inserted between the TCP and the pad terminal isdirectly cohered with some portion of the substrate of the LCD panel.

[0016] Additional features and advantages of the invention will be setforth in the description which follows and in part will be apparent fromthe description, or may be learned by practice of the invention. Theobjectives and other advantages of the invention will be realized andattained by the structure particularly pointed out in the writtendescription and claims hereof as well as the appended drawings.

[0017] In order to accomplish these objects, the present inventionsuggests a method for manufacturing an LCD panel comprising steps offorming a thin film transistor having a gate electrode, a sourceelectrode and a drain electrode, a gate line connecting the gateelectrode, a source line connecting the source electrode and, a gate padand a source pad formed at the end of the gate line and the source line,respectively on a substrate, depositing a passivation layer covering thethin film transistor and the pads and, exposing some portions of thegate pad, the source pad and some portion of the substrate between theeach pad. Also, an LCD panel according to the present inventioncomprises a substrate, a plurality of gate line on the substrate, aplurality of data line crossing with the gate line, a gate pad and adata pad at the ends of the each gate line and the source line,respectively, and a plurality of hole exposing some portions of thesubstrate between the each pad.

[0018] These and other aspects, features and advantages of the presentinvention will be better understood by studying the detailed descriptionin conjunction with the drawings and the accompanying claims.

BRIEF DESCRIPTION OF THE ATTACHED DRAWINGS

[0019] A detailed description of embodiments of the invention will bemade with reference to the accompanying drawings, wherein like numeralsdesignate corresponding parts in the several figures.

[0020]FIG. 1 is a perspective view of a conventional active matrixliquid crystal display device;

[0021]FIG. 2 is a cross-sectional view of the conventional active matrixliquid crystal display device;

[0022]FIG. 3 is a cross-sectional view of the structure of ACF;

[0023]FIGS. 4a and 4 b are cross-sectional views showing the TCP beingconnected to the LCD pad using an ACF;

[0024]FIG. 5 is a cross-sectional view of the passivation layer of theLCD panel is being peeled off according to the shrinking force of thefilm;

[0025]FIG. 6 is a cross-sectional view of the passivation layer at theedge portion of the LCD panel being peeled off according to theshrinking force of the film;

[0026]FIG. 7 is a plan view of an LCD panel according to the presentinvention;

[0027]FIGS. 8a-8 e are cross-sectional views showing a method formanufacturing the LCD panel according to the present invention; and

[0028]FIG. 9 is an enlarged plan view of the pad portion of the LCDpanel according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029]FIG. 7 shows a plan view of an active panel according to apreferred embodiment of the present invention. On a transparentsubstrate 101, a first metal layer 211 is formed by depositing aluminumor aluminum alloy, as shown in FIG. 8a. A second metal layer 213 isformed by depositing a metal having a high melting point such asmolybdenum, tantalum, tungsten or antimony sequentially on the firstmetal layer 211. These stacked metal layers 211 and 213 are patterned ina first mask process to form a gate electrode 111, a gate line 113 and agate pad 115. Once these stacked layers 211 and 213 are patterned by awet etching method, then the gate materials, such as the gate electrode,the gate line and the gate pad have a cross sectional shape of which thewidth of the second metal layer 213 is narrower than that of the firstmetal layer 211. A plurality of the gate line 113 is arrayed andfabricated in a vertical direction. The gate electrode 111 is derivedfrom the gate line 113 and disposed at a corner of the designed pixel.The gate pad 115 is disposed at the end of the gate line 113, as shownin FIGS. 7 and 8a.

[0030] On the substrate having the gate material stacked with the first211 and the second metal layer 213, an inorganic insulating materialsuch as a silicon nitride is deposited or a silicon oxide or an organicinsulating material such as BCB (bezocyclobutane) or acrylic resin iscoated to form a gate insulating layer 117. An intrinsic semiconductormaterial, such as a pure amorphous silicon, and an extrinsicsemiconductor material, such as an impurity doped amorphous silicon, aresequentially deposited thereon. These stacked layers are patterned usinga second mask process to form a semiconductor layer 133 and a dopedsemiconductor layer 135. They are disposed on the gate insulating layerover the gate electrode 111, as shown in FIGS. 7 and 8b.

[0031] On the substrate 101 having the doped semiconductor layer 135,and the metal layer made of any suitable material, such as chromium orchromium alloy, are patterned using a third mask process to form asource electrode 121, a drain electrode 131, a source line 123 and asource pad 125. A plurality of the source lines 123 perpendicularlycrossing each gate line 113 on the gate insulating layer 117 is arrayedin a horizontal direction. On one side of the doped semiconductor layer135, the source electrode 121 derived from the source line 123 isformed. On the other side of the doped semiconductor layer 135, thedrain electrode 131 facing the source electrode 121 is formed, as shownin FIGS. 7 and 8c.

[0032] On the substrate 101 having the source materials (for example,the source electrode, the drain electrode, the source line and thesource pad), an inorganic material such as silicon nitride or a siliconoxide is deposited or an organic material such as BCB (benzocyclobutene)or acrylic resin is coated to form a passivation layer 137. Using afourth mask process, some portions of the passivation layer 137 coveringthe source pad 125 and the drain electrode 131 are removed to form asource contact hole 161 and a drain contact hole 171. And some portionsof the passivation layer 137 and the gate insulating layer 117 coveringthe gate pad 115 are removed to form a gate contact hole 151. Someportion of the passivation layer 137 and the gate insulating layer 117covering the substrate 101 between the each gate pad 115 and each sourcepad 125 are removed to form holes 193 exposing the substrate 101, asshown in FIGS. 7 and 8d.

[0033] On the passivation layer 137, a transparent conductive materialsuch as ITO (Indium Tin Oxide) is deposited and patterned using a fifthmask process to preferably form a pixel electrode 141, a gate padterminal 157 and a source pad terminal 167. The pixel electrode 141connects to the drain electrode 131 through the drain contact hole 171.The gate pad terminal 157 connects to the gate pad 115 through the gatecontact hole 151. The source pad terminal 157 connects to the source pad125 through the source contact hole 161, as shown in FIGS. 7 and 8e.

[0034]FIG. 9 is a plan view illustrating the pad portion of the activepanel according to the present invention. Some portions of the gateinsulating layer 117 and the passivation layer 137 between theneighbored pad portions are removed to form the holes 193 exposing thesubstrate 101. It is preferable to form many small holes in order toenhance the adhesion effect of the TCP to the pad according to thepresent invention, as shown in FIG. 9. It is especially preferable toform a large hole 193 a at the edge portion because the gate insulatinglayer 117 and the passivation layer 137 have a weak cohering force atthe edge portion.

[0035] According to the present invention, when the TCP is attachedusing ACF on the pad terminal of the LCD panel, some portions of the ACFare directly attached to the substrate exposed through the holes so thatthe TCP and ACF are firmly cohered to the LCD panel. Therefore, it ispossible to prevent the TCP and ACF from peeling off from the substrate.

[0036] While the description above refers to particular embodiments ofthe present invention, it will be understood that many modifications maybe made without departing from the spirit thereof. The accompanyingclaims are intended to cover such modifications as would fall within thetrue scope and spirit of the present invention.

[0037] The presently disclosed embodiments are therefore to beconsidered in all respects as illustrative and not restrictive, thescope of the invention being indicated by the appended claims, ratherthan the foregoing description, and all changes which come within themeaning and range of equivalency of the claims are therefore intended tobe embraced therein.

What is claimed is:
 1. A flat panel display device comprising: asubstrate; a plurality of lines formed above the substrate, each linehaving a pad; a first layer positioned above the substrate to cover atleast a portion of the substrate, wherein the first layer exposes thepad of the each line and defines at least one opening near the pad, theopening having a depth lower than the surface of the first layer; and asecond layer having a first part and a second part, wherein the firstpart is affixed to the pad to provide an electrical signal to the lineand the second part is affixed to the opening defined in the first layerto enhance adhesion between the first and second layers.
 2. The flatpanel display device of claim 1, wherein the first part of the secondlayer is a conductive portion and the second part is an insulatingportion.
 3. The flat panel display device of claim 1, further includinga third layer disposed between the second layer and the first layer,wherein the third layer affixes the first part to the pad and the secondpart to the substrate through the at least one opening defined in thefirst layer.
 4. The flat panel display device of claim 2, furtherincluding a third layer disposed between the second layer and the firstlayer, wherein the third layer affixes the conductive portion to the padand the insulating portion to the substrate through the at least oneopening defined in the first layer.
 5. The flat panel display device ofclaim 2, wherein the second layer is a tape carrier package.
 6. The flatpanel display device of claim 3, wherein the third layer is ananisotropic conductive film.
 7. The flat panel display device of claim1, wherein the at least one opening defined in the first layer extendsto the substrate.
 8. The flat panel display panel of claim 1, whereinthe first layer defines a plurality of openings for securing the secondlayer with the first layer.
 9. The flat panel display panel of claim 1,wherein the first layer is an insulating layer.
 10. An active panel of aliquid crystal display device comprising: a substrate; a gate lineformed on the substrate; a gate pad formed at the end of the gate line;a gate insulating layer covering the gate line and the gate pad; asource line crossing the gate line on the gate insulating layer; asource pad formed at the end of the source line; a passivation layercovering the source line and the source pad; a gate contact holeexposing the gate pad; a source contact hole exposing the source pad,wherein the passivation layer defines at least one hole exposing atleast a portion of the substrate between the gate pad and the sourcepad.
 11. The active panel of claim 10, further comprising: a gateelectrode derived from the gate line; a semiconductor layer formed onthe gate insulating layer over the gate electrode; a source electrodederived from the source line and making ohmic contact with a first partof the semiconductor layer; a drain electrode making ohmic contact witha second part of the semiconductor layer; a drain contact hole exposingthe drain electrode; a gate pad terminal connected to the gate padthrough the gate contact hole; a source pad terminal connected to thesource pad through the source contact hole; a pixel electrode connectedto the drain electrode through the drain contact hole; and a connectorincluding a conductive pad connected to the gate pad and the source padand an insulating film affixed to the at least a portion of thesubstrate exposed through the hole.
 12. A method for manufacturing anactive panel of a liquid crystal display device, comprising steps of:providing a substrate; fabricating a plurality of lines above thesubstrate, each line having a pad; forming a first layer above thesubstrate to cover at least a portion of the substrate, wherein thefirst layer exposes the pad of the each line and defines at least oneopening near the pad, the opening having a depth lower than the surfaceof the first layer; and forming a second layer having a first part and asecond part, wherein the first part is affixed to the pad to provide anelectrical signal to the line and the second part is affixed to a bottomsurface of the opening defined in the first layer to enhance adhesionbetween the first and second layers.
 13. The method of claim 12, whereinthe first part of the second layer is a conductive portion and thesecond part is an insulating portion.
 14. The method of claim 12,further including forming a third layer between the second layer and thefirst layer, wherein the third layer affixes the first part to the padand the second part to the substrate through the at least one openingdefined in the first layer.
 15. The method of claim 13, furtherincluding forming a third layer disposed between the second layer andthe first layer, wherein the third layer affixes the conductive portionto the pad and the insulating portion to the substrate through the atleast one opening defined in the first layer.
 16. The method of claim13, wherein the second layer is a tape carrier package.
 17. The methodof claim 14, wherein the third layer is an anisotropic conductive film.18. The method of claim 12, wherein the at least one opening defined inthe first layer is fabricated to extend to the substrate.
 19. The methodof claim 12, wherein the first layer defines a plurality of openings forsecuring the second layer above the first layer.
 20. The method of claim18, further including forming a third layer between the second layer andthe first layer, wherein the third layer affixes the first part to thepad and the second part to the substrate through the at least oneopening defined in the first layer.